Duty‐Cycle Distortion Tolerable Frequency Detector for Reference‐Less Clock and Data Recovery

This letter proposes a duty‐cycle‐distortion (DCD)‐tolerant frequency detector (FD) for reference‐less clock and data recovery (CDR) systems. The proposed FD employs a two‐unit‐interval(2‐UI) windowing to suppress false frequency‐up/down(FUP/FDN) events caused by DCD‐induced 1‐UI variation in conventional XBBPDs. Circuit‐level closed‐loop simulation with a 10‐Gb/s PRBS31 input shows that the proposed FD eliminates incorrect FUP/FDN triggering at the target frequency and achieves stable frequency acquisition within 5–6 µs under up to 10% DCD.