A 28.4–30.5‐Gb/s Reference‐Less Full‐Rate Clock and Data Recovery With Current Mismatch Elimination in 28‐nm CMOS

This paper reports a full‐rate reference‐less bang‐bang clock and data recovery (BBCDR) circuit with current mismatch elimination functionality. Specifically, a simplified frequency acquisition loop (FAL) based on lock detection (LD) is proposed to achieve efficient and robust frequency acquisition without the need to determine the polarity of frequency errors. This technique eliminates the need for multiphase clocks and additional high‐speed samplers, significantly saving power and area. In addition, a compact current mismatch elimination circuit is introduced to mitigate the impact of the bang‐bang phase detector (BBPD) metastability characteristic. Prototyped in 28‐nm CMOS, the BBCDR circuit automatically tracks a PRBS‐11 none‐return‐to‐zero (NRZ) input between 28.4 and 30.5 Gb/s, with the total chip area being 0.12 mm 2 . At a rate of 30.5 Gb/s, the peak‐peak jitter of the recovered clock and data are 2.25 and 7.31 , respectively, with a core power efficiency of 1.80 pJ/bit.