A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate CDR Circuitwith One-Tap DFE

A 20Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision-feedback equalizer (DFE) is presented. To widen the timing region of the clock, a foreground calibration circuit is presented to calibrate the threshold voltage of the comparator. It enhances the jitter tolerance (JTOL). This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.103mm 2 . The total power is 47.6mW and the calculated power efficiency is 2.38pJ/b at 20Gb/s. The measured high-frequency JTOL is larger than 0.2UI <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</inf> and the settling time of this calibration circuit is less than 12.7μs..