An Energy-Efficient FPGA-Based CNN Accelerator with Dual-Multiply Packing and Ping-Pong Buffering for Real-Time Object Detection

Real-time deployment of modern object-detection networks on edge devices is challenging because of limited compute resources, external-memory bandwidth, and strict power constraints. To address these issues, this paper presents a host–FPGA collaborative accelerator for quantized YOLOv5n on a Xilinx Zynq-7100 platform. The proposed design includes a modular multi-operator neural processing unit supporting seven atomic operators, a Dual-Multiply Packing (DMP) scheme to improve DSP48E1-based INT8 convolution density, a cache–compute–cache dataflow with global ping-pong buffering to overlap DMA transfers and computation, and a Multi-Quantization Domain Alignment (MQDA) pipeline to preserve accuracy at Add and Cat fusion nodes. Implemented at 200 MHz, the prototype achieves 24.617 ms FPGA-side forward-inference latency, 36.686 ms end-to-end single-frame latency, 27.2 FPS system-level performance, 182.8 GOPS equivalent throughput, and 8.536 W on-chip power consumption, corresponding to 21.42 GOPS/W. Experimental results also show that INT8 quantization causes only limited accuracy degradation, while MQDA improves quantized detection accuracy by reducing cross-domain fusion error. These results demonstrate that the proposed architecture provides an effective balance among throughput, energy efficiency, hardware cost, and quantized accuracy for real-time edge object detection.