A Low-Noise Low-Offset Rail-to-Rail Amplifier with Full-Band Frequency Compensation

A low-noise low-offset rail-to-rail amplifier with full-band frequency compensation is presented in this work.To balance stability, power consumption and size performance, the design realizes full-band frequency compensation by adopting an enhanced hybrid topology, in which transconductance capacitance feedback compensation (TCFC) is nested within a multipath nested Miller compensation (MNMC) topology. The proposed design employs a three-stage amplifier to improve DC-gain, using parallel complementary differential pairs with current feedback loop and a class-AB stage to achieve stable rail-to-rail input and output. The PMOS-dominant differential transistor pairs of input stage are operated in sub-threshold region, enabling lower input-referred thermal noise and much lower power consumption. Furthermore, a source degeneration structure is incorporated to further suppress thermal noise, along with a trimming logic to minimize the offset voltage. Finally, a slew-rate enhancement (SRE) circuit is further implemented to ensure that large output currents can be supplied under low quiescent current conditions, thus enabling a full rail-to-rail output swing. Fabricated in 0.18[Formula: see text]m CMOS process technology, the layout occupies an area of 890[Formula: see text]m×495[Formula: see text]m. Operating under a 5V power supply, the pre-layout simulation results demonstrate that the amplifier achieves rail-to-rail input/ output functionality with an open-loop gain of 154 dB, phase margin of 69.53°, and gain-bandwidth product (GBW) of 9.9 MHz. The equivalent input noise is 8.5 nV/ [Formula: see text] at 1 kHz, with a common-mode rejection ratio of 109.456 dB. The power supply rejection ratios is 114.697 dB. The measured positive and negative slew rates reach 7.35 V/[Formula: see text]s and 8.37 V/[Formula: see text]s.