Key result
A VLSI Hamming neural network chip using 0.35 μ CMOS technology was designed and simulated to classify non-binary input patterns for intercardia tachycardia classification.
Describes the design and simulation of a VLSI Hamming neural network chip for arrhythmia classification in implantable cardioverter defibrillators.
Preliminary VLSI simulation indicates hardware viability for arrhythmia classification; leaves open clinical efficacy and safety testing.
The implantable cardioverter defibrillators (ICDs) detect and treat dangerous cardiac arrhythmia. This paper describes a VLSI neural network chip to be implemented using 0.35 μ CMOS technology which acts as an intercardia tachycardia classification system. The Hamming network used to classify non binary input pattern and also reduce impact of noise, drift and offset inherent in analog application. Simulation result using HSPICE and level 49 parameters (BSIM3V3) that verify the functionality of circuit are presented.
No takes yet. Share an insight, caveat, or question.
GHANAVTI et al. (2009) studied Cardiac arrhythmia. VLSI Hamming neural network chip was evaluated on Circuit functionality verification via simulation. A VLSI Hamming neural network chip using 0.35 μ CMOS technology was designed and simulated to classify non-binary input patterns for intercardia tachycardia classification.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: