Analysis of the Power Delivery Path From the 12-V VR to the Microprocessor

This paper offers a thorough analysis of the power delivery path. Based on the power delivery path model, the current slew rate of each loop is derived. The relationship between the inductor current slew rate of the voltage regulator (VR) and the bandwidth is also derived. Then, the level of the voltage spike across the capacitors of each loop is determined, after which the relationship between the bandwidth and the capacitance can be plotted. We find that for today's power delivery structure, the bulk capacitors can be eliminated as long as the bandwidth is pushed beyond 350 kHz. The experimental results of a 2-MHz two-stage 12-V VR verify this analysis.