An analog signal processor ASIC for portable ECG monitoring was implemented in 0.5 μm CMOS, consuming 30 μW from a 2 V supply, achieving a data compression factor of 7 and 4x power reduction.
This paper presents the design and implementation of an analog signal processor (ASP) ASIC for portable ECG monitoring systems. The ASP ASIC performs four major functionalities: 1) ECG signal extraction with high resolution, 2) ECG signal feature extraction, 3) adaptive sampling ADC for the compression of ECG signals, 4) continuous-time electrode-tissue impedance monitoring for signal integrity monitoring. These functionalities enable the development of wireless ECG monitoring systems that have significantly lower power consumption yet that are more capable than their predecessors. The ASP has been implemented in 0.5 μm CMOS process and consumes 30 μW from a 2 V supply. The noise density of the ECG readout channel is 85 nV/√Hz and the CMRR is better that 105 dB. The adaptive sampling ADC is capable of compressing the ECG data by a factor of 7 and the heterodyne chopper readout extracts the features of the ECG signals. Combination of these two features leads to a factor 4 reduction in the power consumption of a wireless ECG monitoring system. Furthermore, the proposed continuous-time impedance monitoring circuit enables the monitoring of the signal integrity.
Yazıcıoğlu et al. (Wed,) conducted a other in ECG monitoring. Analog signal processor (ASP) ASIC was evaluated on Power consumption, noise density, CMRR, and data compression. An analog signal processor ASIC for portable ECG monitoring was implemented in 0.5 μm CMOS, consuming 30 μW from a 2 V supply, achieving a data compression factor of 7 and 4x power reduction.
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