An efficient and reconfigurable architecture for RC5

RC5 is a widely used symmetric block cipher which has a variable word size, number of rounds, and length of secret key. In this paper, we propose an efficient and reconfigurable hardware architecture for the RC5 block cipher implementation. The design can be reconfigured according to the different application requirements with variable parameters. It is simulated in Verilog HDL and implemented on Xilinx FPGA. Comparison shows that it has high throughput and low hardware complexity