Two approaches to high throughput processors are Chip Multi-Processing (CMP) and Simultaneous MultiThreading (SMT). CMP increases layout efficiency, which allows more functional units and a faster clock rate. However, CMP suffers from hardware partitioning of functional resources. SMT increases functional unit utilization by issuing instructions simultaneously from multiple threads. However, a wide-issue SMT suffers from layout and technology implementation problems. We use
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Burns et al. (2001) studied this question.
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