Design of a low-power RISC-V based intelligent endoscopy detection processor: EndoRISC-V

Capsule endoscopy provides a non-invasive method for examining the gastrointestinal tract, but it generates more than 50,000 images which need several hours of manual examination. Real-time image processing in wearable receiver units could reduce the errors, but demand high computational throughput with low power and latency constraints. Standard CPUs are built for general-purpose workloads and fail to handle the mathematical computations and data throughput of image processing operations. This paper presents EndoRISC-V, a two-level reconfigurable RISC-V Harvard architecture consuming 124 mW total power at 100 MHz operation. This processor features: (i) Switchable execution units during runtime allowing selection between standard ALU instructions and image operations that include four extended instructions (MAXPOOL, Histogram Equalization, Sobel-X, and Sobel-Y), providing 4.29 \(×\) throughput improvement over baseline RISC-V with 6.75 \(×\) speedup for down-sampling operations; (ii) Pipelined architecture with variable pipeline depth between 3 and 5 stages, achieving 16.3% cycle reduction for image-intensive workloads in low-power mode. The design was built using Verilog HDL while the synthesis and implementation was performed on Xilinx Artix-7 FPGA. The design consumes 2,971 LUTs and 1,858 flip-flops at 100 MHz with 6.898 ns positive timing slack. Real-time processing capabilities were validated on the Kvasir Gastrointestinal dataset through edge-based polyp detection, which processed 8 \(×\) 8 regions with a 3.45 \(μ\) s execution time at 60.4 frames per second using 640 \(×\) 480 resolution, exceeding the clinical requirement of 2–4 frames per second by a 15.1 \(×\) margin. The system uses 124 mW of power to achieve 0.428 nJ energy efficiency per classification. The custom image processing unit requires 115 LUTs, representing 3.9% of total design space, to deliver 3.77 \(×\) better performance than standard RISC-V.