Vertical 3D Phase-Change Memory with Metallic Liner for Enhanced Resistance Drift Suppression

Among non-volatile memories (NVMs), phase-change memory (PCM) has emerged as a promising candidate for various applications owing to its fast switching speed, scalability, and multilevel-cell (MLC) capability. Nevertheless, resistance drift in the amorphous phase remains a critical obstacle to reliable MLC operation. Although metallic liner integration has been shown to mitigate this issue in planar PCM structures, its direct application to vertically stacked 3D architectures pursued for high-density memory requires re-optimization of the liner parameters. Here, we integrate a metallic liner into a vertically stacked 3D PCM structure and conduct finite element method (FEM) simulations to identify a target thickness range of 15–25 nm based on the trade-off between resistance drift suppression and ON/OFF ratio. Based on these results, a 4-layer metallic liner-integrated vertical PCM was fabricated and electrically characterized, achieving a significant reduction in the RESET state drift coefficient at 25 ℃ while maintaining data retention comparable to the conventional device. This suppression extended across all programmed states, confirming the reliability of multilevel operation. However, the continuous metallic liner along the vertical stack introduces a potential parasitic leakage path between adjacent layers. To evaluate this effect, inter-layer read-current coupling was quantified through a simplified 1 × N stack model extended to 64 layers, with the projected mean error remaining below 1 %. These results demonstrate the device-level feasibility of metallic liner integration in vertically stacked PCM with enhanced resistance drift suppression.