Understanding and Mitigating Interlayer Thermal Crosstalk in 3D Vertical Phase‐Change Memory

Three‐dimensional vertical phase‐change memory (3D vertical PCM) provides a device‐level route toward vertically integrated phase‐change storage, yet vertical stacking converts cell‐level thermal confinement into a stack‐level reliability constraint. Here, interlayer thermal crosstalk is investigated in a dual‐layer Hf‐doped Ge─Sb─Te 3D vertical PCM device by constructing an operation‐ and state‐dependent disturbance matrix. The monitoring cell is initialized in either the crystalline low‐resistance state or the amorphous high‐resistance state, while READ‐, SET‐, and RESET‐level pulse trains are applied to the adjacent programming cell. READ and SET produce limited disturbance, whereas RESET dominates interlayer thermal perturbation. The amorphous high‐resistance state exhibits the highest susceptibility, showing a pronounced resistance decrease under adjacent RESET excitation. Qualitative electrothermal simulations attribute this selectivity to localized RESET heating and transient vertical heat spreading across stacked layers. Paired‐pulse programming temporally redistributes the RESET thermal budget by decoupling rapid selected‐layer heating from delayed interlayer heat spreading. This strategy preserves the thermal response required for selected‐cell programming while suppressing heat transfer to the monitoring layer. Electrical measurements confirm that paired‐pulse programming improves post‐disturbance resistance retention from <40% to >85%, demonstrating thermal‐budget engineering as an effective strategy for enhancing the reliability of vertically integrated 3D vertical PCM devices.