RTL-Level Power Optimization of CNN Accelerators via Clock Gating and Sparsity-Aware MAC Suppression on FPGA

Convolutional Neural Network (CNN) accelerators are widely deployed in edge Artificial Intelligence (AI), embedded vision, and object detection systems, but their hardware designs often incur significant power consumption due to intensive multiply–accumulate (MAC) operations, frequent register toggling, memory transactions, and persistent signal switching. This study examines Register Transfer Level (RTL)-level power optimization of a CNN accelerator on a Field-Programmable Gate Array (FPGA) using three design approaches: a baseline, a Local Explicit Clock Gating (LECG) + Memory Split scheme, and a sparsity-aware scheme. The LECG + Memory Split approach reduces redundant sequential and memory-switching operations, while the sparsity-aware scheme further minimizes arithmetic operations on zero-valued operands. FPGA power measurements on a Xilinx ZCU102 platform reveal a total power decrease from 3.644 W in the baseline to 2.775 W with LECG + Memory Split and 2.442 W with sparsity-aware optimization. This achieves up to a 32.99% reduction in total power without increasing Digital Signal Processing (DSP) block or Block Random Access Memory (BRAM) usage. The findings confirm that integrating control-based, memory-aware, and data-aware RTL methods enhances the power efficiency of CNN accelerators while maintaining the main compute and memory architectures.