Low-Leakage CMOS Design Using Dynamic Threshold Scaling for IoT Devices

The rapid proliferation of Internet of Things (IoT) devices has intensified the demand for ultra-low power and energy-efficient VLSI circuit designs. One of the major challenges in nanoscale CMOS technology is the significant increase in leakage power, which adversely affects battery life and system reliability in always-on IoT applications. This paper presents a low-leakage CMOS design using Dynamic Threshold Scaling (DTS) to effectively minimize static power dissipation while maintaining high performance. The proposed approach dynamically adjusts the threshold voltage (Vthₜₕth) of MOS transistors based on the operating conditions, enabling a trade-off between leakage reduction and switching speed. In the proposed architecture, adaptive body biasing and voltage control mechanisms are integrated to modulate the threshold voltage in real time. A 45 nm CMOS technology node is considered for implementation and simulation. Experimental results demonstrate that the proposed DTS-based CMOS design achieves a leakage power reduction of approximately 38.7%, along with a 22.5% improvement in energy efficiency compared to conventional fixed-threshold CMOS circuits. Additionally, the design maintains a delay variation within 8%, ensuring reliable performance for IoT workloads. The proposed method is particularly suitable for battery-operated and energy-constrained IoT devices such as wearable sensors, smart home systems, and remote monitoring units. Overall, this work provides a scalable and efficient solution for next-generation low-power CMOS circuit design in IoT ecosystems.