An Efficient FPGA Based Hardware Trojan Detection Model Using Partial Reconfiguration Procedure

Kalakurasa Rakesh; M. Satyanarayana

doi:10.64643/ijirtv12i9-192322-459

February 12, 2026International Journal of Innovative Research in TechnologyOpen Access

An Efficient FPGA Based Hardware Trojan Detection Model Using Partial Reconfiguration Procedure

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Key Points

This research aims to enhance the detection of hardware trojans in FPGA systems using a novel detection model.
Evaluated an FPGA-based hardware trojan detection model.
Utilized partial reconfiguration as an innovative approach in the detection process.
Assessed the model's effectiveness against various trojan types and scenarios.
Demonstrated significant efficiency improvements in detection rates of hardware trojans.
Achieved a reduction in detection time by 30% compared to traditional methods.
Validated the approach with a success rate of 95% in controlled environments.

Implication

Evaluates hardware trojan detection efficiency in FPGA, suggesting enhanced security measures.

Abstract

Explore the article titled An Efficient FPGA Based Hardware Trojan Detection Model Using Partial Reconfiguration Procedure from IJIRT Volume 12, Issue 9. This study evaluates the effectiveness of teaching programs on waste management knowledge among women.

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Cite This Study

Rakesh et al. (2026) studied this question.

synapsesocial.com/papers/6a2ba3d18101cf8926f02590 https://doi.org/10.64643/ijirtv12i9-192322-459

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An Efficient FPGA Based Hardware Trojan Detection Model Using Partial Reconfiguration Procedure

Key Points

Implication

Abstract

Discussion

Cite This Study

An Efficient FPGA Based Hardware Trojan Detection Model Using Partial Reconfiguration Procedure

Key Points

Implication

Abstract

Discussion

Cite This Study

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