Influence of Device Structure and Manufacturing Thermal Budget on Channel Release Module in GAA NSFET and Process Optimization

In logic device development, gate-all-around nanosheet field-effect transistors (GAA NSFETs) are widely regarded as the future mainstream architecture. Due to an innovative stacked-channel design, a novel process module of channel release has been introduced, posing significant challenges to device manufacturing. The channel release quality plays a decisive role in the device’s turn-on voltage and operating speed. Meanwhile, the complex interferences are undoubtedly brought by diverse structures and manufacturing thermal budgets of GAA NSFETs. Here, the non-plasma gas etching, which is not yet widely used in the current industry, is adopted for channel release. The influences of nanosheet width, spacing, and annealing conditions on the etching process are systematically studied. A SiGe/Si etching selectivity as high as 87 is achieved. With increasing channel width, a downward trend in the single-sided damage in the central region of Si nanosheets is shown. At >100% over-etching, the Si single-sided damage in structures with different channel spacing is controlled below 1 nm. The intensified diffusion of Ge elements in the SiGe layer and a gradual slowdown of the SiGe etching rate are caused by increasing the annealing temperature. The root mean square (RMS) value of the channel surface roughness is reduced from 0.087 to 0.069 nm by adding the *H radical pretreatment into the process. These findings provide valuable guidance for developing a channel release etching process with high selectivity, low damage, a stable process window, and low fabrication difficulty.