Design of a Low-Power FSM-Controlled SRAM-Based MAC Architecture with Reduced Switching Activity

Multiply-Accumulate (MAC) units are important building blocks of modern digital systems, especially in signal processing, machine learning, and embedded applications. Traditional MAC structures are generally based on parallel processing methods, which have high hardware complexity and power consumption. This paper deals with the design and analysis of an FSM-controlled power-efficient SRAM-based MAC architecture for sequential computation. The proposed design uses dual SRAM blocks to store input data and weights, so that the structured memory access is available and the data movement overhead is reduced. The computation flow is controlled by an FSM-based control mechanism to ensure deterministic operation and to reduce switching activity by enable-based gating. The architecture is parameterized for scalability and is implemented in Verilog HDL. Functional verification is carried out using simulation, and results show correct operation in several test cases. The proposed approach provides lower hardware complexity and higher energy efficiency compared to the conventional parallel MAC designs and is suitable for low-power embedded and signal processing applications. The simulation is performed using Vivado in 28nm technology.