Adaptive Energy—Accuracy Trade-Offs in Configurable MAC Architectures for AI Acceleration

Energy efficiency has become a primary bottleneck in hardware platforms supporting machine learning workloads, particularly as modern inference and training tasks demand sustained high-throughput computation. This challenge is further amplified in energy-harvesting and intermittently powered systems, where the available energy budget varies over time. This work introduces a run-time configurable multiply–accumulate (MAC) architecture that dynamically adjusts arithmetic precision to match instantaneous energy availability. The proposed design relies on an internally adaptive multiplier based on bit-level logic compression, enabling controlled modulation of power consumption while preserving numerical robustness. Crucially, the MAC maintains a fixed external operand interface, allowing for seamless precision adaptation without operand reformulation or datapath disruption. The architecture is implemented in System Verilog and evaluated using both ASIC synthesis in a 90 nm CMOS technology and FPGA deployment. Experimental results demonstrate approximately a fourfold improvement in power–delay product (PDP) relative to full-precision operation, with only limited degradation in inference accuracy.