Hybrid approximate arithmetic circuits with merits balance for CNN inference

– Multiply-Accumulate (MAC) units dominate computation and energy use in deep neural network accelerators, comprising over 98% of operations in modern convolutional workloads. Exploiting the error resilience of convolutional neural network inference, this paper proposes hybrid approximate MAC architectures. These selectively approximate key datapath modules—partial product generation, reduction, and accumulation—for balanced trade-offs in power, delay, area, and accuracy. A novel radix-8 Booth pre-encoding scheme is introduced to support both signed × signed and unsigned × signed operations using a single-bit MSB extension, simplifying sign handling and reducing compressor requirements. Approximation is further applied by eliminating complex ±3 Booth terms, introducing energy-efficient approximate half adders, full adders and 4:2 compressors guided by rigorous error-metric analysis, and employing a hybrid accumulator that combines an exact Han–Carlson prefix adder in the MSBs with a lightweight Lower-OR Adder in the LSBs. Four configurable AxMAC variants are proposed to explore fine-grained accuracy–efficiency trade-offs. Synthesized in 45 nm CMOS technology, the proposed designs achieve up to 43.5% delay reduction, 73.6% area savings, and 46.5% power reduction compared to an exact radix-8 Booth MAC, while maintaining low normalized error metrics. Extensive error analysis and CNN inference evaluation on CNN models across MNIST, CIFAR, and ImageNet datasets demonstrate average accuracy losses below 3.5%. Finally, integration into a systolic array confirms the scalability and effectiveness of the proposed AxMAC architectures for energy-efficient deep learning accelerators.