Self-Heating and Channel Geometry Effects in Vertically Stacked CFETs: a TCAD-based Analysis

Complementary Field Effect Transistors (CFETs) are emerging as a promising solution to overcome the scaling limitations of advanced Complementary Metal–Oxide–Semiconductor (CMOS) technologies by vertically stacking n-type and p-type devices within a compact 3D architecture. However, the confined geometry intensifies Self-Heating effects (SHE), which significantly impact electrostatic integrity and carrier transport. This study investigates the influence of channel width variation and self-heating on the electrical behavior of vertically stacked CFETs using calibrated TCAD simulations. Key performance parameters including drain current, threshold voltage, subthreshold swing (SS), and drain-induced barrier lowering (DIBL) are analyzed under varying structural and thermal conditions. The results reveal that SHE increases the lattice temperature by up to 50 K, resulting in a 17–20% reduction in drive current and a noticeable degradation in transconductance. Channel geometry optimization and reduced doping concentration effectively mitigate thermal degradation while maintaining high current drivability. The study provides valuable design insights for realizing thermally robust CFETs suited for ultra-low-power and high-density integration in sub-3 nm technology nodes.