Polyhedral Compute-Memory Architecture with Distributed High-Bandwidth Interconnect – Version 2: System Integration and Software Co-Design

This paper presents Version 2 of our polyhedral compute-memory architecture, extendingthe materials and thermal foundation established in Version 1 [1] with a completesystem-level design. We retain the icosahedral compute unit and separate polyhedralmemory unit, but now introduce: (i) a distributed memory controller hierarchy withface-local controllers and an internal network-on-chip, (ii) a topology-aware addressingmodel `[Face ID][Region][Offset]`, (iii) quantitative bandwidth estimates (10–80 TB/s)based on NbP interconnects from v1, (iv) an extended MMU for topology-aware addresstranslation, and (v) operating system and compiler co-design for NUMA-like memoryzones, data locality, and dynamic page migration. This version transforms the physicalconcept into a functional architecture, addressing memory bandwidth bottlenecks withoutaltering existing DRAM technologies.