Power Integrity Analysis and Evaluation of a Dual-Interposer HBM Structure

High-bandwidth memory (HBM) faces critical power integrity challenges in high-stack configurations due to elongated power delivery paths and increased parasitic inductance. This paper proposes a dual-interposer HBM architecture with an interposer–HBM stack–interposer configuration, integrating an additional top interposer embedded with chip capacitors. This topology redesigns the HBM’s power distribution network, reducing PDN impedance, and this technology enables bidirectional vertical power supply to DRAM chips during moments when they require current. The PDN impedance is systematically compared with a conventional trench-capacitance-enhanced structure (Structure A) and a deep-trench-capacitance-enhanced structure (Structure B). Results show that at 0.1–11.2 GHz, the proposed structure reduces peak PDN impedance by 66.41% and 65.7% versus Structures A and B, respectively, and decreases the loop inductance of the top-layer DRAM chip by 66.71%. The top interposer’s redistribution layer forms a parallel-plate capacitor complementing the embedded chip capacitors, achieving wideband impedance suppression. Without modifying existing protocols, this architecture provides a system-level PDN optimization strategy for high-stack HBM, offering quantitative insights for capacitor selection and layout design.