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Engineering study demonstrates enhanced bandwidth and thermal efficiency in 12-high and 16-high memory stacks, indicating superior scalability over microbump packaging.
A 12-high (12-Hi) die stack using low temperature SoIC bonding and stacking technology is presented and demonstrated for the application of HBM. The daisy chains in the 12-Hi structure incorporating over ten thousand TSVs and bonds are tested. Liner I-V curves are obtained to demonstrate the good bonding and stacking quality. The electrical link from a base logic die to top DRAM is built up to study the bandwidth and power consumption. Compared to μbump technology, the bandwidth for 12-Hi and 16-Hi structure using the SoIC technology shows the improvement of 18% and 20%, respectively and the power efficiency demonstrates the improvement of 8% and 15%, respectively. Also, the thermal performance for the 12-Hi and 16-Hi SoIC-bond structures are improved by 7% and 8%, respectively. Based on the proposed technologies, the scalability of bond pitch to sub-ten μm and die thickness to be thinner is prospected.
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Tsai et al. (2020) studied this question.
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