Transient Stability Analysis of Grid-Forming Inverters Incorporating Detection Delays in Active-Power Reference Reduction Strategies

Reducing the active-power reference of grid-forming inverters during voltage sags is an effective approach for maintaining transient synchronism. However, its performance critically depends on the detection delay preceding derating activation. Existing studies commonly assume instantaneous control response and rarely establish a quantitative stability boundary associated with detection delay. To address this issue, this paper develops a multi-stage Lyapunov energy framework for evaluating the critical detection delay, defined as the maximum admissible delay that still guarantees convergence to the post-derating stable equilibrium. A three-stage transient model is established to describe pre-fault operation, the detection-delay interval, and post-derating dynamics. The post-derating stage is characterized by an energy-based admissible region, while the delay stage is evaluated through transient energy evolution across stages. Simulation and hardware-in-the-loop results show that severe voltage sags and weak-grid conditions substantially reduce the critical detection delay, whereas properly coordinated virtual inertia, damping, and derating depth can enlarge the transient stability margin. Under the standard operating condition, the admissible delay is approximately 41–42 ms. The proposed framework provides a quantitative basis for coordinating low-voltage ride-through derating strategies with fault-detection timing in grid-forming inverter systems.