Performance requirements in critical real-time embedded systems continue to grow steadily, while energy management constraints are becoming increasingly significant. To meet this challenge, only multi-core processors can provide a viable solution. However, using such processors presents major difficulties in systems that require guaranteed real-time behaviour. Due to interferences caused by the access to shared resources, performance optimization of processing tasks, and the lack of detailed documentation about the internal workings of multi-core processors, the real-time behaviour of applications running on these multi-cores can no longer be assured. With the Open Hardware Group initiative and the rise of RISC-V, new open-source processors are emerging, creating the opportunity to adapt a core (such as CVA6) with the appropriate properties for critical embedded systems. This is the research hypothesis pursued for the past four years by the TRACES team at IRIT, which has modified the CVA6 core to make it temporally predictable and thus formally guarantee the required real-time properties. The initial results led to the submission and acceptance of the ANR-ASTRID PRINTEmPS project (PRedictable and Safe INTErconnect and PRocessor), whose objective is to develop a predictable multi-core processor (demonstrator) and an analysis platform for worst-case execution and response times, compatible with this processor. The project started in January 2023. During the first year of the project, we have started by identifying a representative case-study: quadcopter stabilization software. This software is responsible for maintaining the balance and orientation of the drone during flight by continuously adjusting motor speeds based on sensor feedback (e.g., gyroscopes, accelerometers). It implements control algorithms, such as PID controllers, that process real-time data to issue precise commands to each of the four motors. Using four separate threads—one per motor—on a quad-core processor allows for parallel execution of motor control tasks, closely mimicking the real-time requirements of an actual drone. This setup is ideal for evaluating the real-time performance and determinism of a quad-core processor, as it tests the processor's ability to handle synchronized, latency-sensitive workloads with interferences. This case study will also verify the hardware design of the multi-core processor and its analysis platform (WCET and WCRT).
Rioux et al. (Mon,) studied this question.