A 0.5–67 GHz Wideband Static 1:2 Frequency Divider in an InP DHBT Technology with Core Transistors Scaling Optimization

This paper presents a 0.5–67 GHz static 1:2 frequency divider implemented in a commercial 0.7 μm InGaAs/InP DHBT technology. Instead of migrating to a more advanced process or introducing complex speed-enhancement circuits, a selective transistor scaling strategy is adopted, where only the critical switching and latching differential pairs in the CML master–slave core are implemented using 0.5 μm high-fT DHBTs, while the input/output buffers, bias circuits, and non-critical devices remain based on standard 0.7 μm transistors. This approach reduces the parasitic capacitances at speed-limiting nodes and improves the high-frequency operation of the divider with minimal circuit and process overhead. The fabricated divider achieves a continuous operating bandwidth from 0.5 to 67 GHz, a full-band input power range from −5 to +10 dBm, a single-ended output power higher than −10 dBm, and an SSB phase noise of −141.03 dBc/Hz at 100 kHz offset with a 30 GHz input. These results demonstrate that selective core transistor scaling provides an effective and practical route for upgrading wideband static frequency dividers on mature InP DHBT platforms.