A Computationally Lightweight Multi-Rate Estimation and Passivity-Based Control Architecture for Sensorless BLDC Fan Drives

This repository contains the preprint manuscript, theoretical proofs, and simulation datasets for the development of a computationally efficient, multi-rate estimation and control architecture designed for small-scale, sensorless Brushless DC (BLDC) motor drives. Conventional sensorless control architectures face strict computational bottlenecks when deployed on standard embedded microcontrollers, particularly when attempting to simultaneously address zero-speed observability, thermal parameter drift, and non-linear aerodynamic load variations. This submission presents a physics-informed framework that resolves these challenges through a structurally decomposed electro-thermo-mechanical approach, intended for standalone embedded applications. Key Technical Contributions: Proxy-State Formulation: A novel state representation that promotes back-EMF components to state variables, strictly preserving observability at exactly $0$ RPM without requiring mechanical state reconfiguration. Interacting Multiple Model (IMM) Fusion: Seamless probabilistic handover between a standstill Unscented Kalman Filter (UKF) utilizing Active Saturation Pulse (ASP) excitation with heavy-tailed Student's-t innovations, and a running Extended Kalman Filter (EKF). Deterministic Thermal Augmentation: Replaces conventional random-walk stator resistance tracking with a first-principles thermodynamic energy balance, preventing long-horizon estimation drift during continuous-duty operation. Passivity-Based Adaptive Control: An Input-to-State Stable (ISS) adaptive PI control law incorporating a passivity-preserving anti-windup mechanism to handle voltage saturation. Multi-Rate Computational Efficiency: By decomposing the estimator into a $10$ kHz fast electrical loop and a $100$ Hz reduced-rate recursive least-squares (RLS) mechanical adaptation layer, the architecture restricts the computational burden to approximately $2902$ FLOPs per cycle, consuming only $35.5%$ of the CPU duty cycle on a standard $170$ MHz STM32G4-class microcontroller.