Power-Efficient Shakti C-Class Processor for DSP Accelerator

The growing demand for energy-efficient embedded and digital signal processing (DSP) systems has increased the need for low-power processor architectures. In synchronous digital systems, unnecessary switching activity and continuous clock propagation contribute significantly to dynamic power consumption. Clock gating has emerged as an effective low-power design technique for reducing redundant switching activity without affecting functional operation. This work presents the integration of a DSP-oriented Multiply-Accumulate (MAC) unit along with clock-gating optimization in the SHAKTI C-Class processor, an open-source RISC-V based architecture. The proposed MAC architecture incorporates operand isolation and enable-controlled operation to support arithmetic-intensive DSP computations while minimizing unnecessary transitions. The design was implemented using Verilog HDL and synthesized using the SCL180 standard-cell library. Synthesis results demonstrate a reduction of 14.5% in leakage power, 15.6% in internal power, 26.5% in switching power, and 16.7% in overall total power consumption compared to the baseline architecture. The optimized design incurs only a 2.8% area overhead and a negligible 0.3% timing degradation, demonstrating an effective trade-off between power efficiency and hardware resources. The results validate the effectiveness of combining clock gating and DSP-oriented MAC integration for developing energy-efficient embedded processor architectures.