Implementation of simplified multilayer neural networks with on-chip learning

In this paper, a new digital architecture of multilayer neural network (MNN) with on-chip learning is proposed. Proposed MNN is designed to have no multiply operation for efficient hardware implementation. The absence of the multiplier makes the circuit size small, thus the proposed MNN is suitable for massively parallel VLSI implementation. To provide the on-chip learning ability, the back-propagation algorithm is modified to have no multiply operation, and the algorithm is implemented with pulse-mode operation. Further, a tri-state function is used as the activate function of neurons so that the multipliers in forward path is replaced by a combination of shift and logical AND operations, which are easily realized by digital circuits. The proposed MNN is implemented on a field programmable gate array (FPGA) and tested. To verify the feasibility of the proposed MNN in the larger application, the MNN design is tested using a pattern recognition problem by computer simulations.