In-memory computing (IMC) architectures have emerged as a promising solution to drastically reduce data movement in artificial intelligence (AI) workloads. However, as IMC performance scales up, meeting the requirements of ultra-low power applications becomes increasingly challenging. Here, an ultra-low power and low overhead charge domain ferroelectric field effect transistor (FeFET) based IMC crossbar macro is proposed, implementing multiply accumulate (MAC) operations. The MAC unit within the macro uses 1FeFET-1R (1F1R) cells to inject current into a shared capacitor, yielding multiple discrete voltage levels. A systematic design space exploration was performed to identify parameters resilient to process variations, enabling robust quantization by the Analog to Digital Converter (ADC). Using an experimentally calibrated compact model of FeFETs, systematic simulations show that a 4-bit-quantized convolutional neural network (CNN) deployed on our proposed 256×256 IMC array achieves 98% accuracy on the MNIST database with a power consumption of 39.6 μW and a peak energy efficiency of 647 TOPS/W. These results pave the way towards practical and ultra-low power edge-AI accelerators.
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Zhao et al. (2026) studied this question.
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