Communication often represents a critical bottleneck in the execution of deep neural networks (DNNs) on artificial intelligence (AI) accelerators. To improve communication efficiency, we propose HT-NoC (High-Throughput Network-on-Chip), a dynamically reconfigurable NoC that adapts its throughput to optimize internal resource utilization, thereby enabling the simultaneous transmission of a larger number of packets. Extensive evaluations across diverse DNN layers demonstrate that HT-NoC consistently outperforms a baseline non-reconfigurable mesh NoC. Specifically, HT-NoC accelerates the propagation of input parameters by up to \ (4\) in fully connected (FC) and pointwise (PW) layers, while reducing dynamic energy consumption by \ (2. 6\). For convolutional (CONV) and depthwise (DW) layers, HT-NoC achieves speedups of up to \ (2. 3\) and energy savings of \ (2. 15\). Finally, when integrated into an AI dataflow accelerator, HT-NoC delivers a \ (3. 2\) speedup over systolic array (SA) -based accelerators in executing feed-forward network (FFN) blocks of Transformers. Importantly, these performance and energy improvements are achieved with minimal area, latency, and energy overheads introduced by the reconfiguration mechanism.
Zhiri et al. (Wed,) studied this question.