Bridging the p-type gap in oxide electronics with 2D semiconductors

Monolithic three-dimensional (3D) integration—collocating logic and memory in the back-end-of-line (BEOL)—offers higher bandwidth, lower latency, and improved energy efficiency for AI, cloud, and edge systems. Pairing two-dimensional p-type semiconductors with oxide n-channel transistors establishes a practical basis for complementary BEOL CMOS. This Review assesses manufacturing-aligned pathways to high-performance 2D p-channel transistors, covering transfer-free low-temperature growth, clean van der Waals contacts, gentle p-doping, and mitigation of crystallization, volatility, and interdiffusion. Recent gain-cell and vertical complementary field-effect transistor (CFET) demonstrations are examined, and a pragmatic outlook for BEOL p-type 2D semiconductors is outlined toward manufacturable, dense, low-power monolithic 3D chips. Taikyu Kim and colleagues evaluate WSe2 and Te as back-end-of-line-compatible p-channel counterparts to n-type oxide transistors for monolithic 3D integration. Recent demonstrations establish these 2D semiconductors as potential candidates for dense, energy-efficient monolithic 3D CMOS architectures.