A Cryptolocker‐Resistant and Reconfigurable Hardware Data Compressor Design for Artificial Intelligence (AI) Applications

In this paper, a reconfigurable hardware data compressor (RHDC) architecture is proposed for reducing the storage requirements in artificial intelligence (AI) applications. The RHDC supports two different compression algorithms: the static deflate algorithm (SDA) and the dynamic deflate algorithm (DDA). A linear‐complexity analysis (LCA) module is designed for the RHDC to dynamically monitor the linearity of the input data. Within the RHDC, the SDA is activated to compress high‐linearity input data, whereas the DDA is mainly responsible for processing low‐linearity input data. This enables the RHDC to achieve both high throughput and compression ratio (CR) while reducing power dissipation. To combat cryptolocker attacks, a novel hardware‐implemented overlap serial detection (OSD) technique is proposed to monitor data randomness in real‐time, protecting the output data of the RHDC from encryption. By utilizing the Ising model to optimize the overall design, the results show that the field‐programmable gate array (FPGA)‐implemented RHDC achieves a 18.8‐Gbps throughput and a 1.98 CR with a 98.2% alarm accuracy against cryptolocker attacks.