A Compact 29‐Level Switched‐Source Inverter With Minimized Semiconductor Devices and Derived Gating Signals

Multilevel inverters (MLIs) are critical for enhancing power quality in medium‐voltage applications, yet traditional topologies often suffer from low reliability and high costs due to the excessive number of power semiconductor switches required to achieve high‐resolution outputs. This paper proposes a novel single‐phase asymmetrical MLI topology capable of synthesizing a 29‐level output voltage waveform with a significantly minimized component count. The proposed configuration utilizes four DC voltage sources and 15 unidirectional power switches to achieve 29‐level output voltage waveform, representing a substantial reduction in active components compared with the conventional cascaded H‐bridge (CHB) inverter which requires 56 switches for equivalent performance. A distinct advantage of this topology is its simplified control architecture; by employing combinational logic to derive complementary switching states, the system requires only eight independent gate driver signals,and other seven is to be logically derived from the eight independent signals, thereby reducing the computational burden on the digital controller. The circuit operation is regulated using the phase disposition pulse width modulation (PD‐PWM) technique to ensure a near‐sinusoidal output with low total harmonic distortion (THD). The theoretical framework is validated through extensive simulations in PSIM and MATLAB/Simulink, and is corroborated by experimental results from a laboratory prototype. Comparative analysis demonstrates that the proposed structure offers a compact, cost‐effective solution with reduced switching losses and installation space requirements suitable for renewable energy integration.