An efficient physics-informed continuous-time model for battery state estimation under power-only runtime observability

Accurate State-of-Charge (SOC) and Time-to-Empty (TTE) estimation for mobile edge devices is fundamentally bottlenecked by a strict power-only observability constraint, as high-frequency synchronous ( V , I ) telemetry is typically inaccessible at the operating-system (OS) level. Traditional Equivalent Circuit Models (ECMs) and deep learning approaches suffer from critical observability failures, unbounded error drift, or prohibitive computational overhead under such incomplete sensing. To bridge this gap, we propose a lightweight physics-informed continuous-time method driven strictly by aggregate power trajectories. Operating without runtime voltage–current telemetry, the method governs SOC dynamics via a charge-conservation Ordinary Differential Equation (ODE) coupled with a quasi-static voltage approximation. The operating envelope is explicitly limited to discharge-only, low-rate ( C r a t e < 0.5 ) mobile baseline loads to ensure the physical validity of this approximation. Within this boundary, the approach mathematically enforces monotonic discharge consistency and captures nonlinear avalanches without unidentifiable polarization parameters. Furthermore, TTE is formulated as a stochastic first-passage hitting time, augmented by Monte Carlo uncertainty propagation for thermal-aware safety. Validation across 7565 dynamic records—spanning Lithium Cobalt Oxide (LCO), Nickel Manganese Cobalt (NMC), and Lithium Iron Phosphate (LFP) chemistries—demonstrates robust chemistry-adapted performance, achieving an SOC tracking Root Mean Square Error (RMSE) of 1.13 × 1 0 − 2 and a TTE Mean Absolute Error (MAE) of 0.72 h. Crucially, the analytical ODE achieves sub-millisecond inference ( 0.5 ± 0.05 ms ) with an O ( 1 ) memory footprint, yielding up to a 23.2 × speedup over contemporary deep learning baselines. This algorithmic efficiency establishes strong theoretical feasibility for future adaptation to constrained edge microcontrollers, pending physical Hardware-in-the-Loop validation.