ISA-Agnostic WCET Co-Analysis of Mixed Hardware/Software Designs

Ensuring safety-critical systems meet timing constraints is essential in aerospace, automotive, and industrial control. Failure can be catastrophic, making worst-case execution time (WCET) determination crucial. Most existing WCET tools require a pre-existing timing model for the target processor and an instruction set architecture (ISA) specific control flow reconstruction algorithm. However, in hardware/software co-design environments, where both ISA and timing behavior evolve, neither a timing model nor the control flow reconstruction algorithm may exist. We introduce a novel method for computing WCET bounds using an instrumented hardware description of a processor 1 . Unlike traditional WCET tools, our method does not require a separate timing model or control flow reconstruction algorithm. Hence, our tool is ISA agnostic, i.e. capable of analyzing different ISAs without changes to the tool itself. Our method employs hardware/software co-analysis to analyze the program binary and processor hardware description as a single system, extending the applicability of WCET analysis to evolving processor designs. We evaluated our tool on five processors reaching a median pessimism of 27.0% and an average tool runtime of 7.81s.