Ultra-High Gain Vertically Stacked WS ₂ NMOS Inverter Enabled by Co-Optimization of Layer Number and Contact Metal

Multilayer two-dimensional (2D) transition-metal dichalcogenides (TMDCs) offer advantages over monolayer (1L), including higher current capability and improved carrier transport. However, direct large-area growth of multilayer TMDCs remains challenging, and most multilayer device studies rely on mechanically exfoliated flakes. Here, we report large-area optimization of multilayer WS 2 field-effect transistors (FETs) formed by sequential stacking of CVD-grown monolayer WS 2 through combined engineering of the number of channel layers and source/drain contact metals. Thickness-dependent characterization reveals that trilayer (3L) WS 2 provides an optimal balance between conduction-path expansion and interlayer transport resistance. Contact engineering further shows that Au electrodes provide superior chemical stability and reduced contact barrier formation. On the basis of these optimized parameters, a large area vertically stacked NMOS inverter was demonstrated using 3L WS 2 FETs as the driving transistor and 1L WS 2 FETs as the load transistor. The resulting inverter exhibits excellent switching behavior and achieves a record-high voltage gain compared to previously reported complementary FETs (CFETs) and vertically stacked NMOS inverters. This work demonstrates that the combined engineering of the WS 2 channel layer number and contact metals enables high-performance vertically stacked inverters and provides a pathway toward scalable, area-efficient three-dimensional integration based on large-area 2D TMDCs.