Large‐Scale Implementation of Vertical Sidewall and Vertical Multi‐Channel WS₂ Nanosheet Field‐Effect Transistors for Area‐Efficient Integrated Circuit

2D materials have emerged as promising candidates for next-generation field-effect transistors (FETs) owing to the atomically thin geometry and excellent electrostatic gate control. Here, double-gate vertical sidewall FETs based on chemical vapor deposition-grown monolayer WS2 are demonstrated and, for the first time, report vertical multi-channel nanosheet FETs (NSFETs). By implementing a dual-step sidewall profile, steep SiO2 surfaces are obtained, which enabled seamless WS2 adhesion and contributed to enhanced device yield. The fabricated vertical sidewall WS2 FETs exhibited good subthreshold swing (SS) and effectively suppressed short-channel effects at channel length as short as 150 nm. Logic gates including inverters, NAND, NOR, AND, OR, and SRAM are integrated using vertical sidewall and planar WS2 FETs, validating the feasibility of area-efficient integrated circuit. Furthermore, improved drive current is achieved in vertical multi-channel NSFETs realized by stacking WS2 channels and employing a gate-all-around-like structure. These results highlight the potential of vertical sidewall FETs for enabling area-efficient, ultra-dense integrated circuits.