A 3.2-Tbit/s PAM4 silicon photonic circuit with O-band scalable WDM I/O architecture for high-bandwidth optical interconnects

Recent advancements in artificial intelligence (AI) and machine learning (ML) have led to increasingly large and complex models, driving significant transformations in modern data centers and high-performance computing (HPC) systems. An urgent need arises for ultrahigh-bandwidth and ultra-high-density communications between compute nodes to support the application demands, which have not been sufficiently supplied. To meet the ever-growing demand for data traffic, the next-generation optical transceivers with embedded silicon photonics (SiPh) in data center and HPC systems are expected to offer the capacities of 800G and beyond. In this article, we propose and experimentally verify a 3.2 Tbit/s scalable O-band silicon photonic wavelength division multiplexing (WDM) I/O architecture based on a hybrid multiplexing scheme combining lattice-filter-based multiplexers (MUXs) and dual-microring-based demultiplexers (De-MUXs), together with integrated photodetectors and a wavelength-locking framework for stabilizing resonator-based devices. The proposed architecture supports 32 wavelength channels with a per-channel data rate of 100 Gbit/s using 4-level pulse amplitude modulation (PAM4), achieving an aggregate data capacity of 3.2 Tbit/s. This is enabled by four 1 × × 8 silicon lattice-filter-based MUXs, four 1 × × 8 dual-microring-based De-MUXs, 32 microring-based modulators, and 32 photodetectors (PDs). We report device-level measurements of key components. These results highlight the potential of all-silicon ultra-high-bandwidth-density terabit-scale optical interconnects and provide a scalable pathway toward future large-scale photonic connectivity for next-generation computing systems.