CMOS Image Sensor With Area-Efficient Block-Based Compressive Sensing

We have designed, fabricated, and measured the performance of a linear and area-efficient implementation of the compressive sensing (CS) method in CMOS image sensors. The use of an active pixel sensor (APS) with an integrator and in-pixel current switches are exploited to develop a compact implementation of CS encoding in analog domain. The intrinsic linearity of APS with integrator circuit guarantees the linearity of the CS encoding structure. The CS measurement process is performed for different blocks of the imager separately. This block-based implementation provides individual access to all the pixels from outside the array, resulting in a scalable design with relatively high fill-factor using only two transistors in each pixel. The CS-CMOS image sensor is designed and fabricated in 130-nm technology for 2 × 2, 4 × 4, and 16 × 16 arrays. The linearity of the extracted measurement is confirmed by the experimental results from 2 × 2 and 4 × 4 blocks. In addition, the block readout scheme and the scalability of the design is examined by fabricating a larger array of 4 × 4 blocks.