Evaluates decoding performance in product codes, suggesting improved efficiency with lower complexity.
Product codes (PCs) are widely used in high-speed communication systems due to their attractive trade-off between error-correction performance and complexity. To further meet the rapidly growing demand for higher data rates, soft-aided hard-decision decoders (SA-HDDs) have been developed. In this paper, we present a reduced-complexity iterative bounded distance decoder with random flipping (RC-iBDD-RF) for PCs, an SA-HDD that improves the decoding performance while preserving low decoding complexity. RC-iBDD-RF introduces an enhanced reliability metric that incorporates channel log-likelihood ratios (LLRs) and memory from previous iterations to guide random flipping. In addition, an error-and-erasure decoding (EaED) module employing fixed filling patterns, rather than randomly generated ones, is used for post-processing to further reduce the residual error rate. The comparisons for BCH-based PCs show that RC-iBDD-RF achieves both performance gain and complexity reduction with only a slight increase in memory requirement. Moreover, the proposed complexity-storage weighted SNR metric confirms its superior complexity-performance trade-off over iBDD-RF.
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Song et al. (2026) studied this question.
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