Machine Learning Based Performance Enhancement Design of 16-bit Hybrid Flash-Binary Search ADC with Comparator Reuse Technique

The design of a 16-bit hybrid ADC with a reuse technique to minimize the chip area, ANN and a 1-D residual CNN model for performance improvement is presented in the research paper. The proposed 16-bit ADC comprised of two 8-bit stages and further the individual 4 bits of these stages are generated using a binary search and flash topology based architecture along with comparator reuse technique for saving the chip area. The designed is further optimized with a sample-and-hold circuit with charge injection reduction technique using a complementary switch. The overall 16-bit ADC architecture carries out the conversion process with only 14 comparators and is implemented in Cadence Virtuoso using 180nm CMOS technology and dissipates 15.71 mW of power when operated with a 1.8 V supply voltage. The pre-layout and post-layout simulation results indicate conversion times of approximately 8.5 ns and 12.5 ns, respectively. The design is finally integrated by incorporating the machine learning CNN model to achieve an ENOB of 12.94 bits, along with an improved 0.02 pJ/con-step Walden figure of merit. The proposed design is highly suitable for a sensor application.