A 28 nm FD-SOI Current-Mode Synaptic Weighting Cell for Low-Complexity Event-Based NILM MLP Inference

This paper presents a digitally controlled current-mode synaptic weighting cell in 28 nm FD-SOI CMOS for low-complexity Multi-Layer Perceptron (MLP) inference in event-based Non-Intrusive Load Monitoring (NILM). A compact bias-free [16,16] MLP is trained offline by backpropagation for fixed-weight feedforward inference. Using 616 ON/OFF events extracted from high-frequency REDD measurements, six appliance classes are characterized by four event-level features: active-power variation, reactive-power variation, current total harmonic distortion of the differential event signature, and event interval. With 16-level input quantization, the model achieves 92.9–93.4% test accuracy and 90.5–90.7% test Macro-F1, requiring 320 weighted-sum branches across two hidden layers. A four-input first-hidden-layer weighted-sum unit is selected as a representative circuit instance. Its computation is mapped to bounded current ranges using current-coded inputs, an 8-bit magnitude-controlled current-mode multiplier, sign-bit current steering, differential current accumulation, and signed-current scaling. The circuit contribution focuses on the weighted-sum datapath, particularly the repeated synaptic weighting cell; activation and complete classifier implementation are outside the scope of this work. Transistor-level PVT and supply-variation simulations validate the signed weighted-sum path, while post-layout extraction evaluates the repeated multiplier cell. The results demonstrate the block-level feasibility of digitally programmable current-mode synaptic weighting for compact event-based NILM inference.