An Analog Neuromorphic On-Chip Training System with IGZO TFT-Based 6T1C 367-State Synaptic Memory Achieving 0.99-R² Linearity and 104-Times Enhanced Retention Time

Emerging synaptic devices are promising for optimizing deep neural network (DNN) accelerators. Training process demands higher-bit weights and inputs, requiring more power and area. Many studies have been conducted to adopt emerging synapses, which efficiently store weights. With multi-bit states analog synaptic devices using Si-CMOS, training becomes challenging due to the leakage of weight values as depicted in Fig. 1 (left and bottom right) [1]. Also, emerging material-based devices may suffer from limited linearity and symmetry, and may not provide conductance range for training. Prior works in DNN training with analog synaptic devices were not fully verified but just tested the individual device rather than the entire array without utilizing the dedicated ICs [2], [3]. Recently, a synaptic array using IGZO TFTs was proposed to enable better compatibility than other emerging devices and lower leakage than Si-CMOS [4–6]. IGZO TFT-based synaptic devices hold promise for applications requiring extended training periods as they can maintain weights for much longer time, but they face challenges related to linearity and symmetry. Furthermore, there is a need for the dedicated wide-range high-precision circuits to hamess these analog memory features.