The rapidly growing demand for neuromorphic computing has driven extensive research shifting from software algorithms to hardware implementations. Among three‐terminal synaptic device candidates, 1T‐DRAM exhibits high‐speed operation but suffers from poor retention, whereas SONOS memory offers long retention but requires high power. To address these limitations, this study proposes a 3D vertically integrated synaptic device utilizing an n–p–n–p–n stacked channel structure that consolidates both volatile and nonvolatile functionalities into a single cell, achieving an ultra‐dense footprint of 4F 2 . By adopting a 3D vertical architecture, the proposed device demonstrates superior integration efficiency compared with conventional planar structures. Furthermore, the unique performance merits of this hybrid structure become particularly pronounced under extended holding times, where transferring stabilized weights from the volatile tier to the nonvolatile SONOS layer eliminates continuous refresh power overhead. To optimize weight modulation, an adaptive dynamic pulse scheme is introduced to secure high state linearity and symmetry across 32 training steps. NeuroSim V3.0 simulations successfully validated its learning capability, demonstrating a high MNIST classification accuracy of approximately 87%. Consequently, the proposed 3D vertical synaptic device serves as a highly promising candidate for next‐generation hardware‐based neuromorphic computing systems.
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Hwang et al. (2026) studied this question.
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