An NPN-based temperature sensor with digital output has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of (3σ ) and a trimmed inaccuracy of (3σ) over the temperature range from to 125 . This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e., correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 from a 1.2-V supply and occupies an area of 0.1 mm 2
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Sebastiano et al. (2010) studied this question.
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