Enhanced Stability of SiZTO TFT Under Positive Voltage and Light Negative Voltage Stress and Modified Hysteresis of the CNTs/SiZTO CMOS Inverter by Si Doping

The property of Si-doped ZnSnO (SiZTO) thin film, thin-film transistor (TFT), and associated CMOS inverter has been optimized by Si doping. Under positive voltage and light negative voltage bias stresses, the SiZTO TFT shows a smaller threshold voltage shift (1.5 and 2.2 V, respectively) than that of the ZTO TFT (4.0 and 4.9 V, respectively). The <tex-math notation="LaTeX">C </tex-math> – <tex-math notation="LaTeX">V </tex-math> hysteresis has reduced from 3.5 V of ZTO TFT to 0.9 V of SiZTO TFT. A good electrical property and stability of SiZTO TFT ensure the construction of high-performance CMOS inverter constructed by SiZTO and solution processed semiconductor single-walled carbon nanotube (CNT) TFT. Moreover, by Si doping, the SiZTO-based CMOS inverter has shown a smaller hysteresis of about 0.17 V and a larger voltage gain of about 44.7 than that of undoped ZTO-based CMOS inverter (voltage gain <tex-math notation="LaTeX">~ </tex-math> 37.5 and hysteresis <tex-math notation="LaTeX">~ </tex-math> 0.31 V). The enhanced stability of SiZTO TFT and CMOS inverter is attributed to the suppression of oxygen vacancy by Si doping. This work provides an efficient strategy to improve the electrical and stability of ZTO/CNTs CMOS inverter and opens a new opportunity for use in wearable electronics and logic circuits.