Demonstrates enhanced throughput of a hardware random number generator, suggesting improved security.
As a fundamental hardware security primitive, true random number generators (TRNGs) offer superior unpredictability over pseudo‐random number generators (PRNGs). However, limited throughput hinders their widespread adoption. Here, leveraging the abundant intrinsic entropy of memristors, we co‐optimize the device switching speed and the sampling method of the entropy extraction circuit. For the device, a bilayer Ti/NbO x /NbO y /Pt (T2NP) threshold switching (TS) memristor, driven by an insulator‐metal transition (IMT) mechanism, delivers the relatively short delay and relaxation time, facilitating both high‐speed and high‐quality random entropy generation among its peers. For the circuit, the conventional nonlinear feedback shift register (NFSR) is augmented with a resistor‐capacitor (RC) delay unit. This forms a dual‐input module comprising the native memristor response and its RC‐delayed counterpart, driving dual‐edge clock sampling to enable dual‐channel output from a single memristor. The optimized TRNG achieves a 4.2 Mb/s throughput with an energy consumption of 1.47 nJ/bit, a 1.89× enhancement in throughput over prior memristor‐based TRNGs. Dual‐image encryption and comprehensive tests confirm the high randomness, reliability, and robustness of the generated bitstreams. This co‐optimized framework underscores significant potential for high‐speed, scalable hardware security in future secure data processing.
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Wang et al. (2026) studied this question.
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