A Low-Power High-Precision Two-Stage FIA Active Adder for Energy-Efficient Sigma-Delta Modulators

The inherent trade-offs among power, linearity, and speed in traditional analog adders constrain the efficiency and performance of high-precision Sigma-Delta modulators. This work proposes a low-power active adder based on a Two-Stage Floating Inverter Amplifier (FIA) applied to a feedforward Sigma-Delta modulator. The structure features: (1) Utilizing Two-Stage FIA cascaded dynamic amplification, it achieves high open-loop gain and summing accuracy with low static power, significantly improving system efficiency. (2) Combined with multi-bit quantization and passive feedforward, it eliminates signal attenuation due to charge sharing in traditional passive networks. This high-precision reconstruction ensures a unity-gain Signal Transfer Function (STF), reducing subsequent quantizer sensitivity requirements and optimizing system-level efficiency. Verifications show the proposed adder, which is designed in SMIC 180nm CMOS, maintains low power while ensuring functionality. Compared to the traditional adder, the power consumption is reduced by 5.29 times. A third-order 4-bit Sigma-Delta modulator integrating this adder achieves 104.62 dB SNDR (8 kHz bandwidth) at 1.8 V. The Figure of Merit (FOM SNDR ) is 175.86 dB, demonstrating high energy efficiency.